“PCI (Peripheral Component Interconnect) bus is a high-performance local bus, which is proposed to meet high-speed data transmission between peripherals and between peripherals and the host. In digital graphics, image and voice processing, as well as high-speed real-time data acquisition and processing and other applications that require high data transmission rates, using the PCI bus for data transmission can solve the problems caused by the low data transmission rate of the original standard bus. Bottleneck problem.
PCI (Peripheral Component Interconnect) bus is a high-performance local bus, which is proposed to meet high-speed data transmission between peripherals and between peripherals and the host. In digital graphics, image and voice processing, as well as high-speed real-time data acquisition and processing and other applications that require high data transmission rates, using the PCI bus for data transmission can solve the problems caused by the low data transmission rate of the original standard bus. Bottleneck problem.
1 PCI local bus features
* High transfer rate: At 33MHz clock frequency, for 32-bit PCI bus, the peak data transfer can reach 132MB/s; 64-bit PCI bus can reach 264MB/s. For a 64-bit PCI bus with a clock of 66MHz, it can reach 528MB/s, which is far greater than the standard ISA’s 5MB/s and EISA’s 33MB/s transfer rate.
*Linear burst transfer: reduces address operations, more efficiently uses the bandwidth of the bus to transfer data, and can ensure that the bus is fully loaded with data.
* Adopt the structure independent of the processor: The device developed by the PCI bus is for PCI and is not limited by the processor, so the design of the PCI device is independent of the upgrade of the processor.
* Automatic configuration function: Each PCI device has 256 bytes of configuration registers, which can realize the plug and play of the device.
* Software transparent: Software drivers use the same command set and state definitions when communicating with PCI devices.
2 Two design methods of PCI interface
The design of the PCI interface must conform to the electrical characteristics and timing requirements defined by the PCI bus specification. There are two implementation schemes of PCI interface: using programmable logic device (FPGA or CPLD) and dedicated PCI interface chip. Using programmable logic devices, you can choose to implement a subset of some PCI specifications. This method is more flexible, but the development is difficult and the development cycle is long. Using a dedicated PCI interface chip can shorten the development cycle and reduce the difficulty of development.
3 Introduction of CY7C90449PV
CY7C09449PV is a PCI master/slave interface chip introduced by Cypress, which conforms to the PCI2.2 specification and can be directly connected to many microprocessors seamlessly. CY7C9449V provides 16KB of dual-port shared memory (SRAM) for transferring data between the PCI bus and the local processor; the I2O message transfer unit has four 32-bit FIFOs to implement message queue and interrupt functions; the maximum local bus clock is 50MHz , a single 3.3V power supply; compatible with 3.3V and 5V PCI signals, using a 160-pin TQFP package.
3.1 Structure of CY7C09449PV
The structure of CY7C09449PV is shown in Figure 1.
3.2 Introduction to function modules
CY7C09449PV provides 64 bytes of PCI header area configuration register space. Among them, Vender ID, Device ID, Revision ID, Header Type and Class Code are used for device identification. The command register (Command) contains device control bits, including allowing memory read and write responses, I/O read and write responses, and so on. The status register (Status) is used to record the status information of PCI bus related events. The base address register 0 (BAR0) provides the starting address of the device in the PCI storage space, 31~15 can be read and written, and informs the system BIOS that the PCI storage space required by this device is 32KB, and any PCI storage space of 31~15 bits consistent with BAR0 Storage space access, CY7C09449PV will affect and accept the transfer. The base address register 1 (BAR1) is the address of the I/O pointer space of CY7C09449PV.
CY7C09449PV provides PCI bus interface, local processor bus interface and I2C serial EEPROM interface, as well as internal 16KB dual-port SRAM, I2O message transfer unit and control register. Data transfers can be performed between the PCI bus and the local processor bus. Both the PCI bus and the local bus can operate on the I2C interface through operation registers.
Data can be exchanged between the PCI bus and the local processor bus through shared dual-port memory. Since the shared memory is a “critical resource”, CY7C09449PV provides 4 arbitration gear bits (L0, P0, L1, P1, L2, P2, P3, P3) in the arbitration register (CRB_FLAGS) for the PCI bus and the local processor. ) for concurrent and mutually exclusive access to shared memory. In order to realize the linear burst transfer, a DMA control register is provided, and both the PCI bus and the local processor bus can start the burst transfer through the DMA control register. To ensure exclusive access to the DMA controller, the DMA control register also provides arbitration flags. The CY7C09449PV provides the local processor with an 8KB memory window mapped to the entire PCI address space. Through this window, the local processor can directly access the PCI address space without going through the shared memory, and the direct access register (DAHBASE) is responsible for the operation of this window.
The I2O message transmission unit of CY7C09449PV has a message queue and interrupt function that conforms to the Intelligent I/O (Intelligent I/O) 1.5 specification, and consists of four 32-bit FIFOs (Inbound Free/Post, Outbound Free/Post) with a depth of 32 and shared memory to achieve. These 4 FIFOs can also be used as general-purpose FIFOs.
Messages between the PCI bus and the local processor can also be transferred via mailboxes. The host transmits the message data to the local processor by writing the Host to Local Data Mailbox (HLDATA) mailbox register, and generates an interrupt flag bit. After the local processor reads the message data, the interrupt flag bit is automatically reset. The local processor can send message data to the host by writing (Local To Host Data Maibox) the mailbox register, and generate an interrupt flag bit. After the host reads the message data, the flag bit is automatically reset.
The initialization data of CY7C09449PV can be saved by connecting EEPROM through I2C interface. These data include configuration information for the PCI bus and the local processor bus. After reset is completed, PY7C09449PV automatically downloads these data before responding to PCI bus and local bus transactions, and performs initialization operations. The I2C port can be read and written through the I2C control register group. The I2C control register group includes 3 registers: I2C command register (NVCMD), I2C read data register (NVREAD), and I2C status register (NVSTAT).
The interrupt controller of CY7C09449PV provides independent interrupt mask and command/status registers for PCI bus and local processor bus: HINT (host interrupt control and status register), LINT (local processing interrupt control and status processor). The interrupt sources are: DMA completion, mailbox, FIFO not empty, FIFO overflow, etc., and an external interrupt pin. Internal resources are listed in Table 1.
Table 1 CY7C9449PV internal resource storage mapping
Storage module offset address[14:0]size/KBI2O register
PCI Direct Access window
Shared dual port memory 0x0000-0x03FF
4 Design scheme of data acquisition system based on PCI and C32
C32 is a 32-bit floating-point DSP with high cost performance and has been widely used in real-time data acquisition and high-speed signal processing. Using CY7C09449PV as the interface chip, the connection between the PCI bus and the C32-based DSP system can be realized.
Connect the RSTOUTD pin of CY7C09449PV with the reset signal of C32, the host can reset C32. The I2C interface pin should be connected to the upper resistor of 2.2KΩ to 10kΩ. When the interface input pin is not in use, it should be pulled up to a high level or grounded. The PLD in Fig. 2 realizes the chip selection of C32 to CY7C9449PV and A/D converter, as well as the signal logic required for the reset BOOT LOADER of C32. EPROM stores C32 programs, SRAM stores data and programs during operation, and EEPROM stores the initialization information of CY7C09449PV.
The system structure is shown in Figure 2.
There are two schemes for transferring the collected data, using FIFO or DMA. FIFO transmission can guarantee sequential transmission, but the transmission efficiency is low, and it is suitable for applications with lower rate requirements. Using DMA for transmission can make full use of the burst transmission capability of the PCI bus, which is suitable for situations where the transmission rate is required to be high. Shared memory is divided into module A and module B. The DSP first writes the collected data into module A, and when the data is full, starts the DMA transfer of module A; at the same time, writes the next collected data into module B, and when the data of module B is full, starts the DMA transfer of module B. DMA transmission, in this way, the cloud can be downloaded in a loop, so that data acquisition and DMA transmission can be carried out in parallel.