“The information of the passive acoustic target is generally mixed in the complex and changeable environmental noise, and the signal-to-noise ratio is low. Traditional target detection is difficult to meet the requirements, and advanced detection and directional positioning algorithms must be used. However, these algorithms have a large amount of calculations, and real-time implementation is difficult. The emergence of the digital signal processor DSP makes it possible to realize the real-time engineering of advanced algorithms.
The information of the passive acoustic target is generally mixed in the complex and changeable environmental noise, and the signal-to-noise ratio is low. Traditional target detection is difficult to meet the requirements, and advanced detection and directional positioning algorithms must be used. However, these algorithms have a large amount of calculations, and real-time implementation is difficult. The emergence of the digital signal processor DSP makes it possible to realize the real-time engineering of advanced algorithms. But the volume, power consumption and reliability of the system have become major problems. This system uses TI’s low-power 5000 series DSP and micro-power 430 series single-chip microcomputers, and adopts a master-slave generalized architecture design. Under the premise of meeting system functional requirements, the volume, power consumption and reliability of the system are determined. It has been greatly improved, and is especially suitable for use in battery-powered equipment with strict power consumption requirements. In addition, rich interfaces are provided to the system, which can make it meet the different requirements of passive target detection systems.
2 The overall design of the system
The main function of the target detection general platform is the acquisition and detection of target information, and the corresponding positioning algorithm processing and subsequent control of target location information. This platform is mainly composed of 4 parts: signal acquisition module, algorithm processing module, system control module and power supply module. The principle block diagram of the platform is shown in Figure 1.
The basic working flow of the system is under the control of the main control single-chip microcomputer, the signal from the sensor is first adjusted to meet the sampling requirements, and then the DSP controls the A/D converter to synchronously sample the signal, and after the A/D conversion The result is sent to the digital signal processor TMS320VC5509 for corresponding algorithm processing, and finally the processing result is passed to the main control machine MSP430 single-chip microcomputer, and then the single-chip microcomputer controls the work of other circuits.
Among them, the signal acquisition module is composed of a 4-channel synchronous sampling A/D converter THS1206, the algorithm processing module is composed of a low-power TMS320-C5000 digital signal processor, and the system control module is implemented by a micro-power MSP430 single-chip microcomputer. The Power Module The TPS73HD-3XX series dual voltage regulator is mainly used to realize the power management of the entire system. The TMS320C5000 digital signal processor works in the slave mode, and the system power management and the working conditions of the slave are controlled by the master MSP430 microcontroller.
2.1 Signal acquisition module
The module uses TI’s A/D converter THS1206. THS1206 is a programmable 12 bit CMOS low-power 4-channel simultaneous sampling A/D converter. The maximum conversion speed is 6 Msample/s, and the maximum power consumption is 216mW. Its speed, resolution, and bandwidth are very suitable for a wide range of applications. . THS1206 can be easily connected with DSP system without any additional devices. There are two 12bit control registers (0, 1) in THS1206, which are used to control its working mode (for specific working methods, please refer to References)). A complete 16 byte deep first in first out (First InFirst Out, FIFO) memory allows data buffer storage, reduces the number of DSP interrupts, and improves the work efficiency of DSP. The internal reference voltage range is 1.5V and 3.5V. The specific hardware connection diagram of THS1206 and TMS-320VC5509 is shown in Figure 2.
THS1206 and DSP are connected through the EMIF of the DSP, and the conversion clock signal is given by the general-purpose timer (Timer) of the DSP, which is convenient for flexible setting of different sampling rates. When TMS320VC5509 is in FULL_EMIF mode, C0 is EMIF.ARE, C2 is EMIF.AWE, and C5 is EMIF.CE1. The chip select CS1 is connected to A13, so the address of THS1206 in TMS320CV5509 is the intersection of CE1 space and A13 being high. In the CE1 segment of TMS320CV5509, its byte address is 0x400000～0x800000, and A13 is required to be high, so its address is: (xxxx,xxxx,xx1x,xxxx,xxxx,xxxxB)∩(0x400000～0x800000), then you can take the word The section address is 0x412000, and the corresponding word address is 0x209000.
According to the specific hardware connection circuit of THS1206 and TMS320VC5509, the A/D interface is initialized. The initialization of THS1206 can be found in references, Here is an introduction to the initial configuration of the DSP interface. The external memory in TMS320VC5509 has 4 chip selection spaces, and they can all be set individually. The settings include memory type, memory width, read and write timing parameters, etc. According to the DSP system clock (the author set it to be 80MHz) and the THS1206 read and write timing requirements, configure the chip select control register CE1_1 as: 0x1009, that is, the memory type is 16bit wide asynchronous memory, the read setup time is 0 clock cycles, read The strobe time is 2 clock cycles, and the read hold time is 1 clock cycle; the chip select control register CE1_1 is configured as: 0x0009, that is, read extended hold time is 0 clock cycles, write extended hold time is 0 clock cycles, write The setup time is 0 clock cycles, the write strobe time is 2 clock cycles, and the write hold time is 1 clock cycle; the chip select control register CE1_1 is configured as: 0x0001, that is, the timeout function is disabled. In this configuration, the DSP can be reliable To communicate with THS1206.
2.2 Algorithm processing module
This module is mainly composed of the core processor TMS320VC5509. It is a new generation of low-power high-performance 16bit fixed-point digital signal processor launched by TI. Its main frequency can reach 200MHz, the cycle efficiency has reached twice that of C54X, and the power consumption is only 1/6 of C54X. It also provides a wealth of peripheral resources, including an external memory interface, which realizes seamless connection with asynchronous memory such as EPROM, SRAM and synchronous memory and other external devices; 3 full-duplex high-speed multi-channel buffered serial ports, DSP can be connected with other DSPs, codecs, etc. through McBSP; in addition, there are universal serial bus, real-time clock, watchdog timer, I2C bus, 10bitADC, multimedia card controller and universal input and output interface. On the basis of taking full advantage of the peripheral resources of the DSP, the author designed a hardware platform with external expansion and complete functions. The principle block diagram is shown in Figure 3.
Based on the signal processing hardware platform designed, the corresponding driver program is designed, including: the EMIF interface program connected with the signal acquisition module, the SPI program communicating with the system control module, the USB driver program that can be connected to the PC, and supporting I2C Communication program and sampling program of ADC integrated with DSP. The program design adopts modularization to facilitate the development and integration of application programs. Based on the above-mentioned software and hardware platforms, further development can be carried out, which can basically meet the needs of various target detection algorithms.
2.3 System Control Module
The system control module is mainly realized by MSP430 single-chip microcomputer. The MSP430 series is a 16-bit hybrid single-chip microcomputer with simplified instruction set and ultra-low power consumption, suitable for battery applications or handheld devices. The author uses the MSP430F149 chip, which integrates with: 8-channel 12bit ADC, 2 16bit timers with 3 capture/compare registers, 2-channel serial communication interface (software selects UART/SPI mode), etc. Based on the specific peripheral resources of the MSP430 microcontroller, the author designed the corresponding system control module hardware platform, and the principle block diagram is shown in Figure 4.
In the above hardware platform, the MSP430 microcontroller can communicate at a high speed through the SPI mode and signal processing module in the serial communication interface; it can communicate with the PC through the USART mode in the serial communication interface 0; it can communicate with the PC through the serial communication interface. The USART mode in 1 communicates with the attitude sensor TCM2 to obtain the attitude information of the platform itself in real time. In addition, the author also connects the 8-channel ADC and 2 16bit timers of the MSP430 single-chip microcomputer. These resources can be used to realize a variety of control functions, such as pre-conditioning and control of the input signal of the signal acquisition module (to meet AD sampling Requirement), the traditional front channel design is generally analog or fixed, using the platform designed by the author, you can easily achieve fully digital front channel control (such as programmable filters and digital AGC, etc.).
Based on the designed hardware, the corresponding driver module was developed, and the SPI communication program of MSP430 single-chip microcomputer and signal processing module, the serial communication program with PC and the serial communication program for obtaining TCM2 attitude information were completed.
2.4 Power module
This module is mainly composed of TPS73HD3XX series dual voltage regulators and some additional circuits. The concrete circuit principle block diagram is shown as in Fig. 5.
The 1.6 V and 3.3V voltages from the THS73HD3XX voltage regulator are supplied to the DSP through a switch circuit controlled by the P5.0 port of the MSP430 microcontroller, and the reset signal of the DSP is connected to the P1.0 port of the MSP430 microcontroller. This design can easily realize the power control of the system, and the power consumption of the system can be effectively controlled because the power consumption of the entire system is mainly on the DSP. The power consumption of the MSP430 single-chip microcomputer is very low. When the DSP is not required, It can be powered down at the right time, and then powered on and reset when needed.
3 System debugging and field test results
On the basis of the above hardware modules and corresponding software, the whole system was debugged. The adaptive parametric model orientation positioning algorithm was implemented on the completed platform, and the anechoic room simulation scale-down orientation test was carried out. The relative error of the distance caused by the pitch angle was ±3.8%, and the relative error of the distance caused by the azimuth angle was ±0.88. %, the accuracy of the algorithm and the real-time processing have reached a satisfactory result. The schematic diagram of the directional positioning and spreading interface is shown in Figure 6.
The author has completed the design of a universal passive acoustic target detection platform, which has powerful peripheral expansion functions, power control, and the average power consumption of the system can be controlled to milliampere level. Due to the use of highly integrated devices, the size of the circuit board is small, 94mm×140mm, which can meet the requirements of practical applications. Interface driver software provides convenience for application system design. The entire software and hardware platform has passed the actual test in the field and can meet the requirements of system design.